Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC

This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC

High-Resolution ADCs Design in Image Sensors

This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power and high-resolution analog-to-digital converters (ADCs) including successive approximation register (SAR) for biomedical imaging application. The results show that with broad range of mismatch error, the SFDR is enhanced by about 10 dB with the proposed performance enhancement technique, which makes it suitable for high resolution image sensors sensing systems

High Linearity SAR ADC for Smart Sensor Applications

This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor application. Monte Carlo simulation results show that capacitive array optimization technique proposed can make the SFDR, SNDR and (Signal-to-Noise Ratio) SNR more concentrated, which means the differences between maximum value and minimum value of SFDR, SNDR and SNR are much smaller than the conventional calibration techniques, more stable performance enhancement can be achieved, and the averaged SFDR is improved from 72.9 dB to 91.1 dB by using the capacitive array optimization method, 18.2 dB improvement of SFDR is obtained with only little expense of digital logic circuits, which makes it good choice for high resolution and high linearity smart sensing systems

A 4-channel 12-bit high-voltage radiation-hardened digital-to-analog converter for low orbit satellite applications

This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5-μm Bi-CMOS technology to achieve the functionality across a wide-temperature range from -55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of -0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from -55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm x 7 mm in total including pads (core active area of 4 mm x 5 mm excluding pads) and consumes less than 525 mW, output voltage ranges from -10 to +10 V

A Horizontal Hall Sensor 3D COMSOL Model

This paper presents a three-dimensional finite element method (FEM) model of horizontal Hall sensor in COMSOL Multiphysics. The model aims to simulate the sensor’s performance in a straightforward way and provides a means to simulate more complex applications with other physics modules. Compared with traditional two-dimensional models, the three-dimensional model is more flexible in designing Hall sensor and shows great significance in verifying the performance of sensors with different materials and geometries. By changing model parameters and comparing simulation results, an optimal design solution can be achieved effectively and economically. The presented Hall sensor achieves a sensitivity of 0.0669 V/(VT). Basic circuit modules of a complete sensor system are also introduced

High-precision adaptive slope compensation circuit for DC-DC converter in wearable devices

This paper presents a high precision adaptive slope compensation circuit for for DC-DC converter in wearable devices. Compared with the traditional adaptive slope compensation circuit, the comparator is used to sample the output voltage and input voltage, which greatly improves the accuracy.In this paper, the circuit is designed in UMC 0.18-μm CMOS Technology and verified by Virtuoso Spectre Circuit Simulator. The simulation results show that the accuracy of the adaptive slope compensation circuit in this paper can reach more than 96%

An external capacitor-less low-dropout voltage regulator using a transconductance amplifier

This paper presents an external capacitor-less NMOS low-dropout (LDO) voltage regulator integrated with a standard CSMC 0.6 μm BiCMOS technology. Over a -55 ∘C to +125 ∘C temperature range, the fabricated LDO provides a stable and considerable amount of 3 A output current over wide ranges of output capacitance COUT (from zero to hundreds of μF ) and effective-series-resistance (ESR) (from tens of milliohms to several ohms). A low dropout voltage of 200 mV has been realised by accurate modelling. Operating with an input voltage ranging from 2.2 V to 5.5 V provides a scalable output voltage from 0.8 V to 3.6 V. When the load current jumps from 100 mA to 3 A within 3 μs, the output voltage overshoot remains as low as 50 mV without output capacitance, COUT. The system bandwidth is about 2 MHz, and hardly changes with load altering to ensure system stability. To improve the load transient response and driving capacity of the NMOS power transistor, a buffer with high input impedance and low output impedance is applied between the transconductance amplifier and the NMOS power transistor. The total area of fabricated LDO voltage regulator chip including pads is 2.1 mm×2.2 mm

Design Considerations of Data Converters for Industrial Technology

This paper presents circuit design considerations of high resolution data converters applied for industrial technology, some important design issues related to filter in analog-to-digital converters (ADCs) are discussed. Whole design flow about filter is given in this work and the design considerations mentioned in this paper are useful for the industrial practice and applications of high resolution ADC, finally, a practical design is illustrated with discussion of ΣΔ modulator

Design of capacitor array in 16-bit ultra high precision SAR ADC for the wearable electronics application

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5+5+6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6μm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step

Method for improving sfdr and sndr of capacitor-resistor combined sar adc by capacitor re-configuration

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter